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Features
* Programmable 33,554,432 x 1-bit Serial Memories Designed to Store Configuration
Programs for Field Programmable Gate Arrays (FPGAs)
* 3.3V Output Capability * 5V Tolerant I/O Pins * Program Support using the Atmel ATDH2200E System or Industry Third Party
Programmers In-System Programmable (ISP) via 2-wire Bus Simple Interface to SRAM FPGAs Compatible with Altera(R) FLEX(R), ExcaliburTM, StratixTM, CycloneTM and APEXTM Devices Cascadable Read-back to Support Additional Configurations or Higher-density Arrays Low-power CMOS FLASH Process Available in 44 PLCC Packages Emulation of Atmel's AT24Cxxx Serial EEPROMs Low-power Standby Mode Single Device Capable of Holding 4 Individual Bit Stream Files Allowing Simple System Reconfiguration * Endurance: 10,000 Write Cycles Typical * Green (Lead and Halide-Free/ROHS Compliant) Package Options Available
* * * * * * * * *
FPGA Configuration Flash Memory AT17F32A
1. Description
The AT17FxxA Series of In-System Programmable Configuration PROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17FxxA Series device is packaged in the 44-lead PLCC see Table 1-1. The AT17FxxA Series Configurator uses a simple serial-access procedure to configure one or more FPGA devices. The AT17FxxA Series Configurators can be programmed with industry-standard programmers, Atmel's ATDH2200E Programming Kit or Atmel's ATDH2225 ISP Cable.
Table 1-1.
Package 44-lead PLCC
AT17FxxA Series Packages
AT17F32A Yes
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2. Pin Configuration
44-lead PLCC
6 5 4 3 2 1 44 43 42 41 40
NC NC NC NC DATA PAGE_EN NC NC NC VCC NC
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NC GND PAGESEL0 NC NC NC NC NC NC NC nCASC/A2
18 19 20 21 22 23 24 25 26 27 28
NC DCLK NC NC NC NC NC NC NC RESET/OE nCS
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36 35 34 33 32 31 30 29
NC SER_EN NC NC READY NC PAGESEL1 NC NC NC NC
AT17F32A
3. Block Diagram
READY
Power-on Reset
Reset
Clock/Oscillator Logic
DCLK
PAGE_EN PAGESEL0 PAGESEL1
Config. Page Select
nCASC(A2) Serial Download Logic
2-wire Serial Programming
DATA
Flash Memory
CE/WE/OE Data Address
nCS Control Logic RESET/OE SER_EN
4. Device Description
The control signals for the configuration memory device (nCS, RESET/OE and DCLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration device without requiring an external intelligent controller. The RESET/OE and nCS pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven Low, the configuration device resets its address counter and tri-states its DATA pin. The nCS pin also controls the output of the AT17FxxA Series Configurator. If nCS is held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the DATA output pin are enabled. When RESET/OE is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of nCS. When the configurator has driven out all of its data and nCASC is driven Low, the device tristates the DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset.
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5. Pin Description
AT17F32A
Name DATA DCLK PAGE_EN PAGESEL0 PAGESEL1 RESET/OE nCS GND nCASC A2 READY SER_EN VCC
I/O I/O I/O I I I I I - O
44 PLCC 2 8 1 20 33 16 17 19 28
I O I - 35 38 41
5.1
DATA(1)
Three-state DATA output for FPGA configuration. Open-collector bi-directional pin for configuration programming.
5.2
DCLK(1)
Three-state clock. Functions as an input when the Configurator is in programming mode (i.e. SER_EN is Low) and as an output during FPGA configuration.
5.3
PAGE_EN(2)
Input used to enable page download mode. When PAGE_EN is high the configuration download address space is partitioned into 4 equal pages. This gives users the ability to easily store and retrieve multiple configuration bitstreams from a single configuration device. This input works in conjunction with the PAGESEL inputs. PAGE_EN must be remain low if paging is not desired. When SER_EN is Low (ISP mode) this pin has no effect.
Notes:
1. This pin has an internal 20 K pull-up resistor. 2. This pin has an internal 30 K pull-down resistor.
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5.4 PAGESEL[1:0](2)
Page select inputs. Used to determine which of the 4 memory pages are targeted during a serial configuration download. The address space for each of the pages is shown in Table 5-1. When SER_EN is Low (ISP mode) these pins have no effect. Table 5-1. Address Space
AT17F32A (32 Mbits) 000000 - 07FFFFh 080000 - 0FFFFFh 100000 - 17FFFFh 180000 - 1FFFFFh 000000 - 1FFFFFh
Paging Decodes PAGESEL = 00, PAGE_EN = 1 PAGESEL = 01, PAGE_EN = 1 PAGESEL = 10, PAGE_EN = 1 PAGESEL = 11, PAGE_EN = 1 PAGESEL = XX, PAGE_EN = 0
5.5
RESET/OE(1)
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on RESET/OE resets both the address and bit counters. A High level (with nCS Low) enables the data output driver.
5.6
nCS(1)
Chip Enable input (active Low). A Low level (with OE High) allows DCLK to increment the address counter and enables the data output driver. A High level on nCS disables both the address and bit counters and forces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the 2-wire Serial Programming mode (SER_EN Low).
5.7
GND
Ground pin. A 0.2 F decoupling capacitor between VCC and GND is recommended.
5.8
nCASC
Cascade Select Output (when SER_EN is High). This output goes Low when the internal address counter has reached its maximum value. If the PAGE_EN input is set High, the maximum value is the highest address in the selected partition. The PAGESEL[1:0] inputs are used to make the 4 partition selections. If the PAGE_EN input is set Low, the device is not partitioned and the address maximum value is the highest address in the device, see Table 5-1 on page 5. In a daisy chain of AT17FxxA Series devices, the nCASC pin of one device must be connected to the nCS input of the next device in the chain. It will stay Low as long as nCS is Low and OE is High. It will then follow nCS until OE goes Low; thereafter, nCASC will stay High until the entire EEPROM is read again.
Notes:
1. This pin has an internal 20 K pull-up resistor. 2. This pin has an internal 30 K pull-down resistor.
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5.9
A2(1)
Device selection input, (when SER_EN Low). The input is used to enable (or chip select) the device during programming (i.e., when SER_EN is Low). Refer to the AT17FxxA Programming Specification available on the Atmel web site for additional details.
5.10
READY
Open collector reset state indicator. Driven Low during power-up reset, released when power-up is complete. (recommended 4.7 k pull-up on this pin if used).
5.11
SER_EN(1)
The serial enable input must remain High during FPGA configuration operations. Bringing SER_EN Low enables the 2-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to VCC.
5.12
VCC
+3.3V (10%).
Notes:
1. This pin has an internal 20 K pull-up resistor. 2. This pin has an internal 30 K pull-down resistor.
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6. FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory. The AT17FxxA Serial Configuration PROM has been designed for compatibility with the Master Serial mode. This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Altera applications.
7. Control of Configuration
Most connections between the FPGA device and the AT17FxxA Serial Configurator PROM are simple and self-explanatory. * The DATA output of the AT17FxxA Series Configurator drives DIN of the FPGA devices. * The DCLK output of the AT17FxxA device drives the DCLK input data of the FPGA. * The nCASC output of a AT17FxxA Series Configurator drives the nCS input of the next Configurator in a cascade chain of configurator devices. * SER_EN must be at logic High level (internal pull-up resistor provided) except during ISP. * The READY pin is available as an open-collector indicator of the device's reset status; it is driven Low while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete. * PAGE_EN must remain Low if download paging is not desired. If paging is desired, PAGE_EN must be High and the PAGESEL pins must be set to High or Low such that the desired page is selected, see Table 5-1 on page 5.
8. Cascading Serial Configuration Devices
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories, cascaded configurators provide additional memory. After the last bit from the first configurator is read, the clock signal to the configurator asserts its nCASC output Low and disables its DATA line driver. The second configurator recognizes the Low level on its nCS input and enables its DATA output. After configuration is complete, the address counters of all cascaded configurators are reset if the RESET/OE on each configurator is driven to its active (Low) level. If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to its inactive (High) level.
9. Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the 2-wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated inside the chip. The AT17FxxA parts are read/write at 3.3V nominal. Refer to the AT17FxxA Programming Specification available on the Atmel web site (www.atmel.com) for more programming details. AT17FxxA devices are supported by the Atmel ATDH2200 programming system along with many third party programmers.
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10. Standby Mode
The AT17FxxA Series Configurators enter a low-power standby mode whenever SER_EN is High and nCS is asserted High. In this mode, the AT17FxxA Configurator typically consumes less than 1 mA of current at 3.3V. The output remains in a high-impedance state regardless of the state of the OE input.
11. Absolute Maximum Ratings*
Operating Temperature.................................... -40C to +85 C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground ..............................-0.5V to VCC +0.5V Supply Voltage (VCC) .........................................-0.5V to +4.0V Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260C ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.
12. Operating Conditions
AT17FxxA Series Configurator Symbol Description Commercial VCC Industrial Supply voltage relative to GND -0C to +70C Supply voltage relative to GND -40C to +85C Min 2.97 2.97 Max 3.63 3.63 Units V V
13. DC Characteristics
AT17F32A Symbol VIH VIL VOH VOL VOH VOL ICCA IL ICCS Description High-level Input Voltage Low-level Input Voltage High-level Output Voltage (IOH = -2.5 mA) Low-level Output Voltage (IOL = +3 mA) High-level Output Voltage (IOH = -2 mA) Low-level Output Voltage (IOL = +3 mA) Supply Current, Active Mode at Freq. Max. Input or Output Leakage Current (VIN = VCC or GND) Commercial Supply Current, Standby Mode Industrial 3 mA -10 2.4 Industrial 0.4 50 10 3 V mA A mA Commercial 0.4 V V Min 2.0 0 2.4 Max VCC 0.8 Units V V V
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AT17F32A
14. AC Characteristics
nCS TSCE RESET/OE TLC CLK TOE TCE DATA TOH TCAC TOH TDF THC THOE TSCE THCE
15. AC Characteristics when Cascading
RESET/OE
nCS
CLK TCDF DATA
LAST BIT FIRST BIT
TOCK nCASC
TOCE
TOOE
TOCE
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16. AC Characteristics
AT17F32A Symbol TOE(2) TCE(2) TCAC(2) Description Commercial OE to Data Delay Industrial nCS to Data Delay
(1)
Min
Typ
Max 50 55 55 60 30 30
Units ns ns ns ns ns ns ns ns
Commercial Industrial DCLK to Data Delay
(1)
Commercial Industrial Data Hold from nCS, OE, or DCLK
(1)
Commercial TOH TDF(3) Industrial(1) Commercial nCS or OE to Data Float Delay Industrial DCLK Low Time
(1)
0 0 15 15 15 15 15 15 20 25 0 0 20 20 10 10 12 12 50 50
ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz s s s s
Commercial TLC Industrial(1) Commercial THC DCLK High Time nCS Setup Time to DCLK (to guarantee proper counting) nCS Hold Time from DCLK (to guarantee proper counting) RESET/OE Low Time (guarantees counter is reset) Maximum Input Clock Frequency SEREN = 0 Write Cycle Time(4) Industrial
(1)
Commercial Industrial
(1)
TSCE
Commercial Industrial
(1)
THCE
Commercial Industrial
(1)
THOE
Commercial Industrial
(1)
FMAX
Commercial Industrial(1) Commercial Industrial
(1)
TWR
TEC Notes:
Erase Cycle Time(4)
1. Preliminary specifications for military operating range only. 2. AC test lead = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels. 4. See the AT17F Programming Specfication for procedural information. 5. The times given are per byte (typical).
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AC Characteristics When Cascading
AT17F32A Symbol TCDF(3) TOCK(2) TOCE(2) TOOE(2) Notes: Description Commercial DCLK to Data Float Delay Industrial Commercial DCLK to nCASC Delay Industrial Commercial nCS to nCASC Delay Industrial Commercial RESET/OE to nCASC Delay Industrial 1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels. 35 ns 40 35 ns ns 55 35 ns ns 50 50 ns ns Min Max 50 Units ns
17. Thermal Resistance Coefficients
Package Type 44J Plastic Leaded Chip Carrier (PLCC) JC [C/W] JA [C/W]
(1)
AT17F32A - -
Note:
1. Airflow = 0 ft/min.
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18. Ordering Information
Memory Size Ordering Code AT17F32A-30BJI 32-Mbit AT17F32A-30BJU Note: 44J-44PLCC Package 44J-44PLCC Operation Range Industrial (-40C to 85C) LHF Industrial (-40C to 85C)
1. The last time buy date is December 29, 2006 for the shaded parts.
Package Type 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC)
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AT17F32A
19. Packaging Information
19.1 44J - PLCC
1.14(0.045) X 45
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45 0.318(0.0125) 0.191(0.0075)
E1 B
E
B1
D2/E2
e D1 D A A2 A1
0.51(0.020)MAX 45 MAX (3X)
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 17.399 16.510 17.399 16.510 14.986 0.660 0.330 NOM - - - - - - - - - - 1.270 TYP MAX 4.572 3.048 - 17.653 16.662 17.653 16.662 16.002 0.813 0.533 Note 2 Note 2 NOTE
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 44J REV. B
R
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Product Contact
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